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| CD4043BCN资料 | |
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CD4043BCN PDF Download |
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File Size : 124 KB
Manufacturer: FSC Description:Reset. M and N bits are all set HIGH. Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divide and N output divide values are latched. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：CD4043BCN 厂 家：FSC 封 装：DIP 批 号：0728+ 数 量：12855 说 明：特价产品★价格优惠!! |
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